Because we will also look at their use case, advantages & disadvantages. Nevertheless the mode of working remains the same.So in this article, we will look at a piece of hardware called the shift register and their modes of operation. Similar to the right-shift PIPO shift register, there can also be a left-shift PIPO shift register as shown by Figure 4. This working is further emphasized in the Table I and Figure 3. This is nothing but right-shift of the data stored within the register by one-bit. At this stage, if the rising edge of the clock pulse appears, then Q 1 appears at Q 2, Q 2 appears at Q 3, … and Q n-1 appears at Q n. output bit of FF 1 (Q 1) appears as the output of OR gate 1 (O 1) connected to D 2 Q 2 = output of O 2 = D 3 and so on. This causes the output bit of each flip-flop to appear at the output of the OR gate driving the very-next flip-flop (except the last flip-flop FF n) i.e. At the same time, these bits also appear at the output pins of the respective flip-flops thus yielding parallel-output data word at the same clock tick.įurther when line is made high, A 1 gates of all the combinational circuits enable while A 2 gates get disabled. This indicates that all the bits of the input data word are stored into the register components at the same clock tick. Thus the bits of the input data word (Data in) appearing as inputs to the gates A 2 are passed on as the OR gate outputs which are further loaded/stored into respective flip-flops at the appearance of first leading edge of the clock (except the bit B 1 which gets directly stored into FF 1 at the first clock tick). Here if line goes low, A 2 AND gates of all the combinational circuits become active while A 1 gates become inactive. In order to convert PIPO register of Figure 1 into PIPO shift register, one has to modify its circuit by adding combinational circuit and control line as shown by Figure 2. However one has to note that the PIPO register shown in Figure 1 is not capable of shifting the data bits. This indicates that both data storage as well as data recovery occur at a single (and at the same) clock pulse in PIPO registers. Further, at the same instant, the bit stored in each individual flip-flop also appears at their respective output pins (Q 1 = D 1 Q 2 = D 2 … Q n = B n). Here each flip-flop stores an individual bit of the data in appearing as its input (FF 1 stores B 1 appearing at D 1 FF 2 stores B 2 appearing at D 2 … FF n stores B n appearing at D n) at the instant of first clock pulse.
Figure 1 shows a PIPO register capable of storing n-bit input data word (Data in). Parallel In Parallel Out (PIPO) shift registers are the type of storage devices in which both data loading as well as data retrieval processes occur in parallel mode.
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